1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly, to a semiconductor integrated circuit device to which an improvement has been made with respect to a layout of wiring for supplying clock signals to circuit blocks constituting the integrated circuit.
2. Description of the Prior Art
For semiconductor integrated circuit devices which perform a desired circuit operation by combining cells for providing the basic function and wiring them, the number of steps and the processing time required to design a layout of the cells and wiring thereof increase exponentially as the semiconductor integrated circuit devices become large scaled. Thus, if an attempt is made to design a layout of the entire integrated circuit at a time, enormous time and labor are required. Then, recently a "hierarchical design technique" is widely used as a method for reducing the time and labor required for the layout design.
The "hierarchical design technique" is a technique by which an integrated circuit is divided into circuit blocks easy to handle in scale and a layout of the circuit blocks and wiring in the circuit blocks is determined except for macro blocks where a layout of devices and wiring thereof is previously determined, then a layout of wiring between all the circuit blocks containing the macro blocks is joined.
In case of designing a layout of a semiconductor integrated circuit device by the hierarchical design technique, it is important to lay out wiring 'between circuit blocks so as to synchronously supply a clock signal from a clock signal source to the clock signal input terminal of each of the circuit blocks. The following specific layout methods are known: Connecting the clock signal source and each of the clock signal input terminals by a separate line, and branching one line connected to the source at an intermediate point and connecting the branches to the clock signal input terminals.
FIG. 2 shows a D-latch flip-flop circuit wherein D is a data signal input terminal, CLK is a clock signal input terminal, Q is a non-inverted signal output terminal, and Q is an inverted signal output terminal. A circuit block B connected to the clock signal input terminal CLK is made up of two inverters INV1 and INV2 connected in series each other.
FIG. 1 shows a layout of devices and wiring in the circuit block B of the flip-flop circuit shown in FIG. 2. In the layout in FIG. 1, both the inverters INV1 and INV2 are of CMOS (complementary metal-oxide-semiconductor) structure.
In FIG. 1, a pair of p-channel MOS (metal-oxide-semiconductor) transistors M1 and M3 are formed in an n-type well W1 formed in a p-type semiconductor substrate and a pair of n-channel MOS transistors M2 and M4 are formed in the semiconductor substrateoutside the well W1. The MOS transistors M1 and M2 constitute the invereter INV1 and the MOS transistors M3 and M4 constitute the invereter INV2.
In an electrocondutive layer nearest to the substrate, polycrystalline silicon layers G1 and G2 are formed in parallel (in the vertical direction in FIG. 1)across the area in which the transistors M1 and M3 are formed and the area in which the transistors M2 and M4 are formed. The polycrystalline silicon layer G1 is used for both gate electrodes and gate electrode wiring of the transistors M1 and M2 and the polycrystalline silicon layer G2 is used for both gate electrodes and gate electrode wiring of the transistors M3 and M4.
Aluminum layers A1, VDD, and GND are formed above the polycrystalline silicon layers G1 and G2. The aluminum layer A1 is connected via contact holes C1 and C2 respectively to the drains of the transistors M1 and M2, via contact holes C5 and C6 respectively to the drains of the transistors M3 and M4, and via contact holes C7 to the polycrystalline silicon layer G2. The aluminum layer VDD is connected via contact holes C3 to the sources of the transistors M1 and M3 and is also connected to a power source. The aluminum layer GND is connected via contact holes C4 to the sources of the transistors M2 and M4 and is also grounded to the substrate. These aluminum layers A1, VDD, and GND exist wi thin one layer.
A line L1 in the circuit block B shown in FIG. 2 corresponds to the polycrystalline silicon layer G1, a line L2 to the aluminum layer A1 connecting the contact holes C1, C2, and C7, a line L3 to the aluminum layer A1 extending to the right of FIG. 1 from the contact holes C7, and a line L4 to the aluminum layer A1 extending toward the right side of FIG. 1 from the contact holes C5.
The clock signal CLK from the clock signal source is supplied to the polycrystalline silicon layer G1 which act as the gate electrodes of the transistors M1 and thereby the transistors M1 and M2 or the inverter INV1 being operated. An output signal of the inverter INV1 is supplied through the aluminum layer A1 to the polycrystalline silicon layer G2 which acts as the gate electrodes of the transistors M3 and M4, thereby the transistors M3 and M4 or the inverter INV2 being operated. An output signal of the inverter INV2 is fed through the aluminum layer A1 to other circuits.
In FIG. 1, it is necessary to connect the polycrystalline silicon layer G1 to a clock signal line (not shown) formed in a wiring area outside the circuit block B and furthermore to a polycrystalline silicon layer for clock signals for other circuit blocks (not shown), so that the ends of the polycrystalline silicon layer G1 are formed protruding from the circuit block B.
A conventional semiconductor integrated circuit device having the above-mentioned layout requires that the polycrystalline silicon layer G1 is connected to the clock signal line formed in the wiring area of circuit blocks, thus the length of the polycrystalline silicon layer G1 becomes long, as a result, a problem of an increase in the cell area arises.
In addition, since the wiring length from the clock signal source to the clock input terminal of each circuit block varies depending on the circuit configuration of the circuit block, another problerm that the clock signal characteristic deviate due to the differences in the clock signal routes and in the load state of the circuit blocks is arises.